封装的DC～4GHz高隔离度吸收式单刀双掷开关(英文)  

DC-4 GHz Packaged High Isolation Non-Reflective SPDT Switches

作　　者：苏黎明[1] 杨洪文[1] 刘宇辙[1] 孙征宇[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2013年第6期419-423,共5页Semiconductor Technology

基　　金：National Natural Science Foundation of China(61271423)

摘　　要：描述了一种基于台湾稳懋(WIN)半导体公司商用0.5μm砷化镓赝配高电子迁移率晶体管工艺的高隔离度吸收式单刀双掷射频开关芯片的设计。设计中使用两级串并结构提高隔离度,加入了吸收电阻减小关断状态下输出端的回波损耗。该芯片采用单电源5 V正压控制,具有使能控制端和全关状态,且控制电平与TTL/CMOS输出电平相兼容。芯片采用8引脚微型小外形封装(MSOP8)形式进行封装,设计中通过三维电磁仿真工具HFSS分析了由封装引入的寄生参数的影响,并提取π型网络进行等效建模。该开关工作在DC～4 GHz频段插入损耗小于1.5 dB,隔离度高于45 dB。仿真结果与实测结果基本一致。The design of a high isolation non-reflective single pole double throw（SPDT） switch chip was described based on a commercial 0.5 μm GaAs pseudomorphic high electron-mobility transistor（PHEMT） process.In this design,a two-stage series-shunt structure was adopted to achieve high isolation and an absorptive resistor was used to decrease return loss in the off-state.With an enable input and an all-off state,this chip was supplied by a single positive voltage of 5 V.The control voltage was compatible with the output of TTL / CMOS circuit.This chip was packaged using 8-lead mini small outline package（MSOP8）.The influence of the parasitic parameters,whtch introduced by the package was analyzed using the 3D electromagnetic（EM） simulator—HFSS,and a network was built to model the parasitic effect.The DC-4 GHz switch has an isolation of more than 45 dB,an insertion loss of less than 1.5 dB.The simulation results are consistent with the measured results.

关 键 词：单刀双掷(SPDT) 赝配高电子迁移率晶体管(PHEMT) MSOP8封装 高隔离度 吸收式 

分 类 号：TN63[电子电信—电路与系统]