5.8GHz低噪声放大器的设计与优化  

Design and Optimization of a 5.8 GHz Low Noise Amplifier

作　　者：王伟印[1] 赵琳娜[1] 沈琪[1] 顾晓峰[1] 

机构地区：[1]江南大学电子工程系轻工过程先进控制教育部重点实验室,江苏无锡214122

出　　处：《微电子学》2013年第3期312-315,共4页Microelectronics

基　　金：国家自然科学基金资助项目(11074280);中央高校基本科研业务费专项资金资助项目(JUDCF10031;JUDCF12032);江苏省普通高校研究生创新计划资助项目(CXLX11_0486)

摘　　要：设计了一种低压、低功耗、输出阻抗匹配稳定的CMOS差分低噪声放大器。基于源极电感负反馈共源共栅结构,提出了基于MOS管中等反型区最小化Vdd.Id的方法,以优化功耗。在共栅晶体管处并联正反馈电容,以提升电路增益。对电路的噪声系数、输出阻抗稳定性、芯片面积等也进行了优化。仿真结果表明,当电源电压为1V,工作频率为5.8GHz时,设计的低噪声放大器的噪声系数为1.53dB,输入回波损耗为-22.4dB,输出回波损耗为-24.6dB,功率增益为19.2dB,直流功耗为4.6mW。A low-voltage and low-power differential CMOS low noise amplifier （LNA） with steady output impedance match was designed. A method to minimize Vad ; Ia of MOS transistor in moderate inversion was proposed based on cascode structure with source inductor feedback, to optimize power consumption of the circuit. A positive feedback capacitor was connected in parallel with common-gate transistor to boost power gain. Noise figure, output impedance stability and chip area were also optimized. Simulation results showed that the proposed LNA, when operating at 5.8 GHz and 1 V supply voltage, had a noise figure of 1.53 dB, an input return loss of -22.4 dB, an output return loss of -24. 6 dB, a power gain of 19.2 dB, and a DC power consumption of 4. 6 mW.

关 键 词：低噪声放大器 共源共栅 中等反型 

分 类 号：TN432[电子电信—微电子学与固体电子学]