SOC验证平台的联合架构设计  

Co-architecture design of SOC verification platform

作　　者：汪洋[1] 耿相铭[1] 

机构地区：[1]上海交通大学电子工程系,上海200240

出　　处：《信息技术》2013年第7期67-71,共5页Information Technology

基　　金：上海市北斗导航与位置服务重点实验室项目(11DZ2260100)

摘　　要：随着芯片行业的不断发展,软件和硬件之间的联系日趋紧密,复杂SOC的设计难点逐渐转移到SoC的验证与调试环节。软硬件协同验证技术作为SOC仿真验证的关键技术,起着越来越重要的作用。文中研究将ARM处理器的指令软件仿真器SocDesigner和RTL硬件仿真器EVE相结合的联合仿真平台架构技术,给出了两个仿真系统通信机制和同步策略,并且以导航模块为例,给出了基于该系统的仿真环境的架构设计和仿真效率的性能测试结果。With the continuous improvement of SOC＇ s integration, difficulty of complex SOC＇ s design gradually shifted to SOC＇ s verification and debugging step. As the key technology of SOC, the hardware and software co-verification technology plays a more and more important role. This paper studies on the co-simulation platform technology which combines ARM instruction simulator and RTL hardware emulator, and gives out its communication and synchronization strategy, then uses navigation module as an example, presents the design of this architecture and the result of simulation efficiency.

关 键 词：SOC 验证平台 联合架构 ESL 硬件加速 

分 类 号：TN492[电子电信—微电子学与固体电子学]