一种低压BiCMOS四象限模拟乘法器的设计  

Design of a Low-voltage BiCMOS Four-quadrant Analog Multiplier

作　　者：管慧[1] 汤玉生[1] 

机构地区：[1]上海交通大学微电子技术研究所,200030

出　　处：《固体电子学研究与进展》2000年第3期270-275,共6页Research & Progress of SSE

摘　　要：提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。A simple low voltage BiCMOS four quadrant analog multiplier using BiCMOS linear region transconductors and pre input circuits is presented. Its basic configuration and design principle are analyzed detailedly. The multiplier is designed in a typical 1.2 μm BiCMOS process and the simulated results are given through SPICE. Simulated results show that for a power supply of ±3 V, the power consumption is less than 2.5 mW, and full scale linear input range is about ±2 V. Both the total harmonic distortion (THD) and non linearity error are less than 0.8% with an input rang up to ±1.6 V. The simulated -3 dB bandwidth is more than 110 MHz.

关 键 词：模拟集成电路 模拟乘法器 四象限 设计 BICMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学]