一种基于DSP和采样ADC的数字锁定放大器  

Digital Lock-in Amplifier Based on DSP and Sampling ADC

作　　者：胡绍民[1] 张广发[1] 

机构地区：[1]国防科技大学应用物理系,长沙410073

出　　处：《数据采集与处理》2000年第2期222-225,共4页Journal of Data Acquisition and Processing

摘　　要：探讨了用 DSP(数字信号处理器 )和采样 ADC(模数转换器 )实现数字锁定放大器的一种方法。在整数个周期内对被测信号进行采样得到信号序列 ,由数学运算得到参考序列 ,通过计算信号序列和参考序列的互相关函数就可实现数字相敏检测。文中还对数字相敏检测的频率特性进行了分析。最后 ,给出了实际设计的数字锁定放大器 ,它的工作频率范围是 10 Hz～ 30 k Hz,实验结果表明 ,可以用它来测量低信噪比的信号。A method of implementing digital lock in amplifier with DSP (digital signal processor) and sampling ADC (analog digital converter) is discussed. Digital signal sequence is acquired through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be realized by calculating the cross correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response of the digital phase sensitive detection is analyzed. Finally, the designed digital lock in amplifier is given, which operates in the frequency range of 10 Hz to 30 kHz. Experimental results show that the digital lock in amplifier can be used for measuring signal with low signal to noise ratio.

关 键 词：数字锁定放大器 DSP ADC 微弱信号检测 

分 类 号：TN722[电子电信—电路与系统] TN911.23