通用的全帧型面阵CCD时序发生器设计方法  

General full frame area array CCD timing generator design method

作　　者：任航[1] 

机构地区：[1]中国科学院航空光学成像与测量重点实验室中国科学院长春光学精密机械与物理研究所,吉林长春130033

出　　处：《红外与激光工程》2013年第7期1842-1847,共6页Infrared and Laser Engineering

基　　金：中国科学院长春光学精密机械与物理研究所二期创新基金(60575025)

摘　　要：介绍了面阵CCD485的内部结构、工作模式,并给出了其基本驱动电路设计。然后通过对面CCD485驱动时序图的分析,分析了全帧型大面阵CCD的正常工作、快速擦除、图像窗口输出和像元合并的驱动时序,提出了一种基于时序细分和有限状态机的通用型全帧型面阵CCD驱动时序发生器设计方法。该方法通过对CCD驱动时序进行分组,将每一组时序的波形划分为若干个基本输出状态,这样CCD各个工作阶段所需的驱动时序都可以由各基本状态组合出来,使用摩尔型有限状态机来描述,将时序驱动器进行了模块化设计。给出了各个模块的具体设计,使时序发生器的设计过程更加简单,最后采用Xilinx公司的Virtex-ⅡPro系列FPGA-XC2VP20、ISE软件平台,设计了CCD驱动时序发生器,并进行了波形仿真分析。输出信号完全满足485芯片的驱动时序要求,证明了该设计方法的有效性。The internal structure and work patterns of the surface array CCD485, were described and thebasic drive circuit design was given. And then through the array CCD485 drive timing diagram analysis,based on the timing segments and the general purpose of the finite state machinetype full frame area arrayCCD drive timing generator, the grouping method by the CCD drive timing, the timing waveforms of eachgroup was divided into a number of basic output state, so that the drive timing of the CCD for each sessioncanby combination of the basic state, and Moore finite state machine to describe the timing-driven modulardesign. The specific design of each module was given, the timing generator of the design process easier, andfinally using Xilinx Virtex-II Pro series FPGA -XC2VP20 and Xilinx＇s ISE software platform, CCD drivetiming generator was designed, and simulation waveform analysis was completed. The output meet the timingrequirements of 485-chip driver, the effectiveness of the design method is proven.

关 键 词：时序细分 有限状态机 面阵CCD 时序发生器 

分 类 号：TN141.9[电子电信—物理电子学]