基于FPGA的高速存储器接口应用开发  

Development of high-speed memory interface application based on FPGA

作　　者：周晓波[1] 李瑞菁[1] 赵强[1] 

机构地区：[1]北京交通大学电子信息工程学院,北京100044

出　　处：《铁路计算机应用》2013年第5期8-11,共4页Railway Computer Application

基　　金：中央高校基本科研业务费专项资金资助(2009JBZ003-4)

摘　　要：为了便捷对复杂时序接口的高速大容量存储介质的应用,本论文提出了一种基于DDRII SDRAM的FIFO特性存储介质接口装置的设计方案。介绍了DDRII SDRAM控制器的原理及实现方法,并基于DDRII SDRAM分时复用技术对存储器接口模块进行了设计,深入分析了接口控制模块各部分的工作原理并对其进行了功能仿真和FPGA的硬件验证。经过测试,高速存储器接口控制模块实现了DDRII内存与FPGA之间的双向数据传输与交互,具有一定的实际应用价值。In order to make convenient interface to the complex sequence interface of high-speed and high capacity storage medium applications, a new design was proposed for the interface device of storage media with FIFO feature based on DDRII SDRAM by this thesis. At first, the principles and implementation of DDRII SDRAM controller were introduced. Then the memory interface module was designed based on the time- sharing technique of DDRII SDRAM. Finally, the principles of the interface controller module was deeply analyzed and implemented by functional simulation through the Quartus II software and FPGA hardware verification. Through stimulation and verification, the high-speed memory interface controller module based on DDRII SDRAM implemented the bi-directional data transfer and interaction between DDRII memory and FPGA, which was with a certain value of practical application.

关 键 词：DDRIISDRAM FPGA FIFO IP核 分时复用技术 

分 类 号：U285[交通运输工程—交通信息工程及控制]