OpenLDI接口的接收器设计及FPGA实现  

Design of Receiver in OpenLDI and Its Implementation with FPGA

作　　者：刘杰[1] 程松华[1] 吴韦建 张永栋[1] 

机构地区：[1]天马微电子股份有限公司研发中心,广东深圳518118

出　　处：《液晶与显示》2013年第4期598-603,共6页Chinese Journal of Liquid Crystals and Displays

摘　　要：利用输入宏单元块设计了LVDS信号转换为CMOS信号的LVDS信号接收器。分析了终端电阻的作用,说明了两种终端电阻使用方法,并重点分析了FPGA内嵌电阻的原理和使用方法。利用DDR技术,研究了3.5倍频的时钟处理7倍频数据的方法,降低了数据的频率;利用数据缓冲器,设计了一种串并转换器。分析了数据对齐的方法和OpenLDI支持的两种信号映射格式;利用数据分配器,通过不同的选择,输出符合两种标准的数据映射格式的数据。结合Xilinx公司的FPGA的时钟处理宏单元块的特点,研究了时钟恢复的方法。利用了周期约束、特定约束、区域约束等约束方法提高程序的可靠性。为了提高整体电路板信号的完整性和降低PCB布局的复杂性,研究了LVDS倒相的方法。The input macro block was used in the design of a signal receiver that turned LVDS signal into CMOS signal. The terminal resistors were analyzed; two methods of using terminal resistance were illustrated. The principle and the using of FPGA embedded resis- tance were emphatically analyzed. DDR technology was used, the method of using 3.5 times clock frequency to process 7 times data was researched and the frequency of data process was reduced. A serial to parallel converter was designed by using the data buffer. The method of data alignment and the two signal mapping formats supported by OpenLDI were analyzed. The data that conforms to the two standard data mapping format was output by using a data distributor. Combining with the characteristics of the Xilinx＇s FPGA clock processing macro block, the method of the clock recovering was researched. The periodic constraints, the spe- cial constraints, and the location constraints were used to improve the reliability of system. In order to improve the signal integrity of the whole circuit board and reduce the complexity of PCB layout, the method of inverting LVDS signals was studied.

关 键 词：开放式LVDS显示接口 LVDS FPGA VERILOG HDL 

分 类 号：TN27[电子电信—物理电子学]