优化的无线多模数字前端加速电路设计方法  

Optimized Design Method for Wireless Multistandard Digital Front End Accelerator

作　　者：赵炎[1] 周晓方[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《小型微型计算机系统》2013年第8期1940-1943,共4页Journal of Chinese Computer Systems

基　　金：国家重大专项(2011ZX03003-003-03)资助;复旦大学专用集成电路与系统国家重点实验室自主项目(11MS003)资助

摘　　要：通信标准的不断发展演进及多样化要求无线通信设备对多模式、软件无线电的支持,同时功耗也成为了此类设备中关键因素.在分析数字前端的基础上,优化了梳状滤波器实现,通过改善传递函数使小数率滤波器等电路可以工作在更低的频率并去除了多级结构中的半带滤波器,从而减少软件无线电下数字前端速率变化电路的功耗,提出了新的用于软件无线电通信设备的数字前端加速电路设计方法.结果表明,本文提出的优化方法能在不降低灵活性、面积、抗干扰能力等性能的条件下减少电路的运算量降低功耗.Development and diversity of communication standards require wireless equipments to support for multistand and software defined radio （ SDR ）, while power consumption becomes a key factor in such equipments. Based on analysis of digital front end （DFE）, this paper optimizes the implementation of cascaded integrated comb filter, and by optimizing the transfer function decreases the working frequency of fractional sample rate conversion filter as well as removes the halfband stage. As a result, power consump- tion of sample rate conversion （ SRC ） in SDR DFE is reduced, and a new design method for SDR DFE accelerator is presented. Re- sults indicate that the presented optimized method could lower the computation load and power consumption without the loss of per- fotlnance like flexibility, area and anti-interference.

关 键 词：数字前端 软件无线电 速率变换 多模式 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]