RFID系统中低功耗JH算法的设计与实现  

Design and Implementation of Low-power JH Algorithm in RFID System

作　　者：周权[1] 王奕[1,2] 李仁发[1,2] 

机构地区：[1]湖南大学嵌入式系统及网络实验室,长沙410082 [2]网络与信息安全湖南省重点实验室,长沙410082

出　　处：《小型微型计算机系统》2013年第8期1944-1948,共5页Journal of Chinese Computer Systems

基　　金：国家自然科学基金项目(61173036)资助

摘　　要：针对资源占用少,功耗要求低的RFID的应用时,低功耗成为哈希算法的一个重要指标.JH算法是SHA-3最后一轮候选算法之一;本文通过改进JH算法中轮函数Rd的算法结构,设计了数据单元为16 bit的JH算法的硬件实现体系结构,提出了一种适应于RFID系统的低功耗JH算法的硬件实现方案.本文以JH-256和JH-512算法为例进行低功耗硬件实现;在Xilinx Virtex-5FPGA平台上,本文的设计分别占用了956 slices和1020 slices,在Altera Stratix III FPGA平台上分别占用了1480 ALUTs和1660ALUTs;在ASIC 0.18μm CMOS库上,当工作频率为100 kHz时,本文的设计分别占用了24797门和26386门,功耗分别为27.8859μW和29.8197μW.实验结果表明,本文JH-256、JH-512算法的硬件实现性能满足RFID系统的应用需求.For small footprint and low-power requirements of RFID （Radio Frequency Identification） applications, lower power con- sumption has become an important indicator of the hash algorithm. The JH algorithm is one of the SHA-3 finalists. Through impro- ving the structure of round function Rd in JH algorithm, this paper proposed a low-power hardware implementation of JH algorithm a- dapt to RFID system, with 16-bit datapath hardware implementation. The proposed low-power JH-256 and JH-512 hardware imple- mentation takes up 956 slices and 1020 slices respectively when ported to Xilinx Virtex-5 FPGA platform, and takes up 1480 ALUTs and 1660 ALUTs respectively when ported to Altera Stratix III FPGA platform. The proposed low-power JH-256 and JH-512 design takes 24797 gate equivalents and 26386 gate equivalents respectively, and cost 27. 8859 p^W and 29. 8197 p.W respectively when using ASIC 0.18 txm CMOS technology running at 100 kHz. Experimental results show that the performance of proposed design meet the application requirements of RFID system.

关 键 词：射频识别 JH 哈希算法 低功耗 硬件实现 

分 类 号：TP316[自动化与计算机技术—计算机软件与理论]