7～13.5GHz单片低噪声放大器设计  

Design of 7-13.5 GHz Monolithic Low Noise Amplifier

作　　者：朱思成[1] 默立冬[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2013年第7期497-501,524,共6页Semiconductor Technology

摘　　要：采用0.15μm GaAs PHEMT工艺,设计了一款7～13.5 GHz宽带低噪声放大器单片集成电路。该单片集成电路可用于点对点、点对多点通信以及测试仪器和测试系统中。电路采用两级级联的放大结构,每级采用自偏压技术实现单电源供电。电路中增加并联负反馈结构,以提高增益平坦度。电路输出后端增加阻性电路,提高部分频段的稳定性,在全频段上满足无条件稳定的条件。在频率为7～13.5 GHz范围内,外加工作电压3 V,对低噪声放大器芯片进行了在片测试,测试结果表明,在带内放大器的噪声系数小于1.6 dB,小信号增益大于17 dB,输入回波损耗低于-12 dB,输出回波损耗低于-15 dB;低噪声放大器芯片面积为2.15 mm×1.15 mm。Based on 0. 15 μm GaAs PHEMT process, a broadband monolithic integrated circuit （IC） low noise amplifier （LNA） with the frequency from 7 GHz to 13.5 GHz is designed. It is used as a LNA or a driver amplifier in point-to-point radios, point-to-muhj-point radios or in test equipment and system. The monolithic amplifier is formed by cascaded two amplification stages.. Each of stages uses self-biased technique to achieve a single power supply. The parallel negative feedback structure is used to improve the gain flatness of the amplifier in circuit, and resistive circuit is used in the output port to improve the stability in some frequency band, which makes it unconditionally stable in all band. In the frequency band 7 - 13.5 GHz, measurement results with ＋ 3 V supply show that the designed LNA has a noise figure below 1.6 dB, the small signal gain is higher than 17 dB, and the input return loss is less than - 12 dB. The output return loss is less than - 15 dB. The LNA chip die Size is 2. 15 mm × 1.15 mm.

关 键 词：赝高电子迁移率晶体管 电子迁移率 晶体管(PHEMT) 低噪声放大器 负反馈 噪声系数 回波损耗 

分 类 号：TN43[电子电信—微电子学与固体电子学] TN722.3