一种高效、可扩展细粒度缓存管理混合存储研究  

Research about Efficient and Scalable Hybrid Memories at Fine-granularity Cache Management

作　　者：姜国松[1] 

机构地区：[1]中国传媒大学信息与通信工程博士后流动站,北京100024

出　　处：《计算机科学》2013年第8期79-82,108,共5页Computer Science

基　　金：湖北省自然科学基金(2011CDC078)资助。

摘　　要：混合主存储器由DRAM构成,它可用作cache来扩展非易失性存储器,相比传统的主存储器能够提供更大的存储能力。不过,要使混合存储器具有高性能和可扩展性,一个关键的挑战在于需要对缓存在DRAM中的数据的元数据(如标签)以一个细粒度的方式进行有效管理。基于这样的观察:利用DRAM缓存行的局部性,将元数据与元数据对应的数据存储在片外缓存中相同的行,使用一个小的缓冲区来只缓存最近被访问的片内缓存行,以降低细粒度DRAM缓存的开销。利用这种细粒度的DRAM高速缓存的灵活性和效率,还开发了一种自适应的策略来选择在数据迁移到DRAM时最佳的迁移粒度。在搭配了512MB的DRAM缓存的混合型存储系统中,建议使用8kB的片上缓存,这样,相比一个传统的8MB的SRAM元数据存储,即使没有考虑大的SRAM元数据存储的能源开销,也可以提升6%以内的性能,以及18%的能效节约。Hybrid main memories are composed of DRAM which can provide much larger storage capacity than tradi- tional main memories used as a cache to scalable non-volatile memories, such as phase-change memory. However, for hy- brid main memories with high performance and scalability, a key challenge is to effectively manage the metadata （e. g. , tags） for data cached in DRAM in a fine- granularity. Based on this observation., storing metadata on off-chip cache line in the same row as their data corresponding to the metadata exploits DRAM row buffer locality, this paper reduced the overhead of fine-grained DRAM cache by using a small buffer to cache chip cache line which has recently been accessed. We also developed an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid me- mory with a 512MB DRAM cache,our proposal using an 8KB on-chip buffer can increase the performance within 6% and save 18% better energy efficiency than a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

关 键 词：缓存 标签存储 非易失性存储器 混合主存储器 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]