基于哈佛结构的单周期堆栈处理器设计  

Harvard Structure-Based Single Cycle Stack Processor Design

作　　者：何凯成[1] 施慧彬[1] 

机构地区：[1]南京航空航天大学计算机科学与技术学院,江苏南京210016

出　　处：《微电子学与计算机》2013年第9期66-70,共5页Microelectronics & Computer

摘　　要：本文设计了一种基于Forth语言的堆栈式16位单周期处理器,该处理器含有深度为32的数据栈、返回栈和哈佛存储结构,其指令集包括29条指令,它的所有指令均在单个周期内执行完成.此处理器在Xilinx公司的XC5VLX110T FPGA开发板上实现的最高时钟频率为162.7MHz.本文首先介绍了此处理器的设计方法、整体结构和指令集,然后分析指令单周期执行的机制,最后给出了处理器的仿真和综合结果及其分析.A 16--bit single cycle stack processor based on Forth programming language is proposed in this paper, the processor has a data stack and a return stack of 32 elements deep, and a Harvard structure storage system. The instruction set of it includes 29 instructions, all of which could be completed within single cycle. When implemented on Xilinx;s XCSVLXll0T FPGA, The processor could run up to 162. 7MHz. The paper first introduces the design principle, architecture and instruction set of the processor and then analyses the strategy of instruction single cycle execution. Finally, it presents the result of hardware synthesizing and software simulation and analysis of it.

关 键 词：FORTH 堆栈 哈佛结构 FPGA 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]