一种改进的汉明码译码器设计与FPGA验证  

Improved Design of Hamming Code Decoder and FPGA Verification

作　　者：田凯[1] 何丽[1] 田方方[1] 梁天宇[1] 

机构地区：[1]重庆邮电大学光纤通信技术重点实验室,重庆400065

出　　处：《电视技术》2013年第17期232-235,共4页Video Engineering

基　　金：国家自然科学基金项目(61071117);重庆市科委项目(2009BB2285)

摘　　要：提出了一种汉明码译码器改进方法,采用串行数据传输和时序优化的方法来降低汉明码译码器占用的资源和成本,并采用模块式的设计方法,设计了编译码系统仿真平台,详细地阐述了整个系统和各个模块的FPGA实现过程。仿真结果表明,设计的译码器复杂度明显降低。An improved method for improving Hamming code decoder is proposed. And a method of serial data transmission and timing optimization is devised to reduce the occupied resource and cost of Hamming decoder. A modular design which is used to design the simulation platform of encoded and decoded system is also proposed in this paper. FPGA implementation process of the entire system and the individual module are detailed described. Simulation results show that the complexity of designed decoder is significantly reduced.

关 键 词：汉明码 译码器 串行数据传输 时序优化 FPGA 

分 类 号：TN919.3[电子电信—通信与信息系统]