LTE中灵活并行无冲突Turbo码交织器的实现  

A Flexible Parallel Non-conflict Interleaver for LTE Turbo Decoder

作　　者：黄跃斌[1] 陈赟[1] 曾晓洋[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2013年第3期334-338,共5页Journal of Fudan University：Natural Science

基　　金：十一五重大专项资助项目(2009ZX01031-002-003-2);国家"863"高技术研究发展计划重点项目(SQ2008AA01ZX1480432);新一代宽带无线移动通讯网重大专项资助项目(2011ZX03003-003-03);国家重点实验室重点资助项目(11ZD0005);上海市教育委员会曙光计划资助项目(11SG07)

摘　　要：为了满足LTE标准中Turbo译码器并行高速的译码要求,设计了一种支持并行译码、存储器访问无冲突的交织器结构.通过对交织器计算公式的推导简化,降低了交织器地址计算的复杂度,同时减少了地址计算单元,只需要一个块地址计算单元即可得到所有存储器的块地址值以及置换网络的控制值.该交织器结构能够实时计算交织地址值,同时灵活性非常高,能够支持多种并行度切换的Turbo译码器.设计的结构在SMIC0.13μm工艺下完成综合,面积为0.023mm2,等效门数为4.5k,最高时钟频率为315MHz.An architecture supporting non-conflict memory access in parallel high speed turbo decoding is proposed to meet the requirement of LTE.The proposed method reduces the address calculation complexity by simplifying the formula for calculation of the QPP interleaver.And it only needs one address calculation unit to get all of the memory addresses and control bits needed by the permutation network.The structure can calculate the address in real time and support the switching of the control signals of the network for Turbo decoders with different parallelism.The design is synthesized with SMIC 0.13 μ m technology with an area of 0.023mm 2 and equivalent gates of 4.5k.The maximum clock frequency of 315MHz is achieved under SS corner.

关 键 词：LTE标准 TURBO码 QPP交织器 灵活 无冲突 

分 类 号：TM934.3[电气工程—电力电子与电力传动]