基于数字延时锁相环的FPGA IO延时管理电路  

A Digital DLL-Based Delay Management Circuit for FPGA's IO Cell

作　　者：王鹏翔[1] 周灏[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2013年第4期497-504,共8页Journal of Fudan University：Natural Science

基　　金：国家"863"高技术研究发展计划(2012AA012001)资助项目

摘　　要：本文提出了一种基于过采样量化器和换挡(Gear-Shift)控制机制的新颖的数字延时锁相环(DDLL),可以嵌入于FPGA芯片IO单元的延时管理系统,实现了IO单元数据通路延时的精确校正,分辨率达到78ps,可调节范围达4ns,满足FPGA芯片对高速串行接口协议复杂时序的兼容.DDLL使用独具特色的过采样量化器,仅使用1bit时间数字转换器(TDC)达到了98dB SNR,等效理论分辨率达16位,并引入了全新的Gear-Shift控制机制,对误差信息合理的加权实现快速精确的锁入,结合2阶巴特沃斯衰减的数字环路滤波器,实现全数字环路控制,较传统模拟延时锁相环,节省了芯片面积和功耗,同时对数字电路所产生的衬底噪声具有更好耐受.DDLL采用65nm数字工艺,嵌入复旦大学自主研发的FPGA芯片,经过后仿验证,锁定时间小于50cycles.A novel digital DLL based on over-sample quantization and Gear-Shift mechanism is proposed. It was embedded in the FPGA＇s IO cell for delay management and achieved precisely controlled delay length. The resolution is 78 ps and the adiustable range is 4 ns, thus the FPGA chip is compatible with high-speed serial interface protocol. The unique over sample quantization using 1 bit TDC achieves 98 dB SNR and equivalent resolution of 16 bits. The novel Gear-Shift control mechanism, processing the phase error information in reasonably weight, achieves fast and accurate locking-in. Combined with a 2-order Butterworth digital loop filter for attenuation, a fully digital control loop is accomplished. The locking-in process is speeded up with better tolerance to the sub-coupling noise generated by the digital circuits around. Fabricated in 65 nm digital process and embedded in the FPGA chip developed by Fudan University, simulation of the DLL demonstrates a lock time of less than 50 cycles.

关 键 词：现场可编程门阵列 过采样量化 Gear-Shift机制 延时锁相环 IO延时管理 

分 类 号：TN402[电子电信—微电子学与固体电子学]