一种带斐波那契译码的高精度电流舵DAC  

High-accuracy current-steering DAC with Fibonacci series decoding

作　　者：李培[1] 尹秋燕[1] 高建军[1] 

机构地区：[1]华东师范大学,上海200241

出　　处：《现代电子技术》2013年第20期136-138,共3页Modern Electronics Technique

基　　金：国家自然科学基金资助项目(61176036)

摘　　要：在设计的电流舵DAC中应用了一种新的译码结构,即斐波那契数列译码结构。通常电流舵DAC设计基于面积和精度的折衷考虑,会采用高位温度计译码,低位二进制译码的分段结构,在此设计的电流舵DAC为进一步提高精度,高位6位仍采用温度计译码,低6位用斐波那契数列译码代替二进制译码。仿真测得DAC转换器的积分非线性误差(INL)为0.5 LSB,微分非线性误差(DNL)为0.28 LSB。在10 MHz采样率下,无杂散动态范围(SFDR)达85 dB。A new decoding structure,Fibonacci series decoding structure,is adopted in a self-designed current-steering digital-to-analog converter（DAC）. The segmented structure is usually adopted in the design of current-steering DAC to balance area and accuracy,in which upper bit uses unary sequence and lower bit uses binary sequence. In order to improve the preci-sion further more,6-bit Fibonacci sequence decoding is used to replace the lower 6-bit binary sequence. The simulation results verify that the differential nonlinearity（DNL）error 0.28 LSB and the integral nonlinearity（INL）error is 0.5 LSB,and the spur free dynamic range（SFDR）reaches 85 dB with the sampling rate of 10 M.

关 键 词：分段式电流舵 DAC 斐波那契数列 译码结构 

分 类 号：TN710-34[电子电信—电路与系统]