提高集成电路ESD防护能力的仿真方法  

Simulation Method of Improving ESD Protection Capability of Integrated Circuits

作　　者：李松[1] 曾传滨[1] 罗家俊[1] 韩郑生[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2013年第10期776-780,共5页Semiconductor Technology

基　　金：国家自然科学基金专项类项目(60927006)

摘　　要：为解决集成电路的全芯片静电防护设计中寄生电阻导致的防护空间压缩问题,提出了一种实用的能够在版图设计过程中提高集成电路静电放电(ESD)防护能力的仿真方法,用于评估和控制ESD电流通路上的寄生电阻,辅助ESD防护设计,预估器件静电防护等级。详细介绍了仿真方法的原理和流程,以0.18μm SOI CMOS工艺制造的静态随机存储器电路为仿真和实验对象,应用此仿真方法,统计寄生电阻值,优化ESD防护设计,并进行ESD测试,记录未优化样品和优化样品的失效电压。通过对比寄生电阻和失效电压,证明降低寄生电阻可获得更好的ESD防护性能,而且器件失效电压和关键寄生电阻值R Vdd之间存在近似线性反比关系。To solve the issue of design window reduction caused by parasitic resistances in the whole-chip electro-static discharge （ESD） protection design of ICs, a practical simulation method for better ESD robustness in layout design was proposed to assess and control the parasitic resistances through the ESD current path, aid the ESD protection design, and estimate the ESD classification level of components. The principle and process of the proposed simulation method have been represented detailedly. All samples, Static Random Access Memory circuits, in the experiment were manufactured with 0. 18 ~m SOI CMOS process. After applying the simulation method for optimizing ESD protection design, the parasitic resistances were counted. The failure voltages of the original samples without optimization and optimized samples under ESD test were recorded. Through comparing the statistics of parasitic resistances of each sample and its failure voltage, it is proved that reducing the parasitic resistances can achieve better ESD performance. Besides, approximately inversely linear dependency exists between the failure voltage of tested samples and the key parasitic resistance Rvd.

关 键 词：全芯片静电放电防护设计 静电放电防护空间 寄生电阻 版图设计 静电放电测 试 

分 类 号：TN406[电子电信—微电子学与固体电子学]