超短沟道高k栅MOSFET寄生电容  

Parasitic capacitance of MOSFET with high k gate and short channel

作　　者：王敏[1] 王保童[1] 柯导明[1] 

机构地区：[1]安徽大学电子信息工程学院,安徽合肥230601

出　　处：《中国科学技术大学学报》2013年第10期822-829,共8页JUSTC

基　　金：国家自然科学基金(61076086);高等学校博士学科点专项科研基金(2103401110008)资助

摘　　要：寄生电容不随器件尺寸的减小而成比例减小,因此对小尺寸器件寄生电容的研究就更有意义.本文首次用矩形等效源建立了MOSFET电势分布二维半解析模型,综合半解析法和特征函数展开法求出二维电势分布函数,并由此得出寄生电容的解析表达式.研究结果表明,减小源/漏区尺寸和栅极厚度可以减小寄生电容,沟道长度的变化对寄生电容几乎没有影响,栅介电常数的增加会使边缘电容减小.模型求解时精度高、运算量小,可直接用于电路模拟程序和器件设计.Parasitic capacitance does not decrease in proportion to the decrease in the size ol the aevtce, anu is thus of greater importance to small size devices. A 2-D semi-analytical model of potential distribution by rectangular source mirror method was proposed for the first time. The semi analytical method and characteristic function expansion method was used to calculate the 2-D potential distribution, from which the capacitance expressions were derived. The result shows that reducing source/drain region size and gate electrode thickness can reduce parasitic capacitance, and channel length exerts little in fluence on parasitic capacitance, and edge capacitance decreases as the gate dielectric constant increases. The model has high precision and smaller calculation, and can be applied directly to circuit simulation programs and device design.

关 键 词：超短沟道 寄生电容 高K材料 半解析模型 

分 类 号：TN386.1[电子电信—物理电子学]