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作 者:LI Jing LIU YuHong DAI YuanJing YUE DaChuan LU XinChun LUO JianBin
机构地区:[1]State Key Laboratory of Tribology,Tsinghua University [2]College of Mechanical and Electrical Engineering,China University of Petroleum (East China)
出 处:《Science China(Technological Sciences)》2013年第11期2847-2853,共7页中国科学(技术科学英文版)
基 金:supported by the Science Fund for Creative Research Groups(Grant No.51021064);the National Natural Science Foundation of China(Grant No.51205226)
摘 要:During the ultra large scale integration (ULSI) process, the surface roughness of the polished silicon wafer plays an important role in the quality and rate of production of devices. In this work, the effects of oxidizer, surfactant, polyurethane pad and slurry additives on the surface roughness and topography of chemical-mechanical planarization (CMP) for silicon have been investigated. A standard atomic force microscopy (AFM) test method for the atomic scale smooth surface was proposed and used to measure the polished silicon surfaces. Finally, compared with the theoretical calculated Ra value of 0.0276 rim, a near-perfect silicon surface with the surface roughness at an atomic scale (0.5 4) was achieved based on an optimized CMP process.
关 键 词:silicon CMP AFM ROUGHNESS
分 类 号:TN47[电子电信—微电子学与固体电子学]
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