A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process  

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

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作  者:许高博 徐秋霞 殷华湘 周华杰 杨涛 牛洁斌 余嘉晗 李俊峰 赵超 

机构地区:[1]Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences

出  处:《Chinese Physics B》2013年第11期536-540,共5页中国物理B(英文版)

基  金:Project supported by the Beijing Natural Science Foundation,China(Grant No.4123106);the National Science and Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)

摘  要:A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ? was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ? was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

关 键 词:HFSION TAN gate-last process planarization 

分 类 号:TN386.1[电子电信—物理电子学] TS94-4[轻工技术与工程—服装设计与工程]

 

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