采用分区域管理的软硬件协作高能效末级高速缓存设计  

An Energy-Efficient Last Level Cache Design Using Software and Hardware Collaborative Region-based Management

作　　者：黄涛[1,2,3,4] 王晶[1,2,5] 管雪涛[1,2] 钟祺[1,2,3] 王克义[1,2] 

机构地区：[1]北京大学微处理器研究开发中心,北京100871 [2]北京大学微处理器及系统教育部工程研究中心,北京100871 [3]北京大学深圳研究生院,深圳518055 [4]公安部网络安全保卫局,北京100741 [5]首都师范大学信息工程学院,北京100048

出　　处：《计算机辅助设计与图形学学报》2013年第11期1658-1667,共10页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家科技重大专项"核高基"(2009ZX01029-001-002);国家"八六三"高技术研究发展计划(2006AA010202)

摘　　要：受"存储墙"和"功耗墙"影响,末级高速缓存污染会造成严重的性能损失和能耗开销.针对单纯基于硬件或软件的传统优化方法无法有效地识别局部性差的数据,且存在一定的优化空间的问题,提出一种软硬件协作的末级高速缓存设计方法.该方法在运行时刻剖视分析程序内不同数据区域的访存行为,并通过相应接口动态地调整每个数据区域的旁路和插入策略,可以在提高处理器访存性能的同时降低其能耗,提高系统的能效性.实验结果表明,与现有的LRU,DIP和DRRIP方法相比,采用文中方法后处理器平均能效性分别提升了17.42%,12.79%和8.15%.Last level cache pollution causes extremely severe performance degradation and energy penalty due to “memory wall” and “power wall”. Hardware-only or software-only last level cache optimization methods can not effectively recognize weak locality data, which means that there is performance improvement space. For addressing above problems, this paper proposes a design of software and hardware collaborative last level cache. This approach profiles the memory behavior of different data regions in a program on runtime and dynamically set the bypass and insertion policy of data regions by corresponding interfaces. While improving the memory access performance of processors, this approach can also reduce energy consumption and improve system energy efficiency. The experimental results show that, in comparison with LRU, DIP and DRRIP, the average energy efficiency of processors is respectively improved 17.42%, 12.79% and 8.15%.

关 键 词：软硬件协作 旁路 插入策略 能效性 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]