基于FPGA和FIFO技术的多串口系统设计与实现  

Design and Implementation of a Muti-channel UART System Based on FPGA and FIFO Technique

作　　者：陈标龙[1,2] 王保成[2] 周江华[2] 

机构地区：[1]中国科学院大学,北京100080 [2]中国科学院光电研究院,北京100080

出　　处：《计算机测量与控制》2013年第10期2835-2837,共3页Computer Measurement &Control

摘　　要：为了同时与多路外设进行串口通信并且提高通信效率,提出了一种基于FPGA和FIFO技术的多串口系统方案;利用一种新的结构框架,可以根据实际工程需要灵活扩展多路串口;该系统由接口模块、寄存器读写模块以及2路内置16字节FIFO的UART模块组成,使用Xilinx ISE开发平台和verilog语言实现;通过软件仿真和实际测试验证了扩展的2路串口均能正常工作,FIFO的使用减少了MCU的中断开销,提高了MCU与外设的通信效率。To communicate with multiple devices and increase the communication efficiency, a mutichannel UART system based on FPGA and FIFO technique is designed. By using a new framework proposed in this paper, several UART channels can be expended at the same time to meet the actual engineering demands. This system contains bus interface module, registers read and write module, 2 UART modules. The whole design is based on Xilinx ISE platform and is realized by using Verilog programming. Software simulation and operation al test have proven the validity and stability of this dualchannel UART system. By using the FIFO, the interrupt cost of the MCU is nota ble reduced and communication efficiency is improved.

关 键 词：FIFO 串口扩展 UART FPGA VERILOG 

分 类 号：TP334[自动化与计算机技术—计算机系统结构]