一种深亚微米复杂芯片物理设计的时序收敛方法  

A Method of Timing Closure in Deep Submicron Physical Design of Complex Chip

作　　者：郑天华[1] 梁利平[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2013年第11期139-142,共4页Microelectronics & Computer

摘　　要：深亚微米工艺下超大规模芯片的物理设计面临很多挑战,互连延时和串扰效应成为影响时序收敛的关键因素.文中介绍了一种采用二次综合、区域约束和串扰预防等措施实现渐进式时序收敛的方法.在65纳米工艺下,通过530万门多核DSP芯片设计验证了该方法.实例设计结果表明,这种方法可以有效地解决互连延时和串扰问题,实现复杂芯片的时序收敛.The deep submicron technology presents lots of challenges to the physical design of VLSI ,the key to timing closure is the interconnect delay and crosstalk . A method based on re-synthesis , region constraints and crosstalk prevent is presented to resolved the timing closure problem of physical design in the paper .The method is verified by design a 5 .3 million gate multi-core DSP chip in 65nm technology .The design example demonstrate that the method efficiently solves the interconnect delay and crosstalk ,and achieves timing closure .

关 键 词：深亚微米 时序收敛 连线延时 串扰效应 

分 类 号：TN43[电子电信—微电子学与固体电子学]