一种缓解NBTI效应引起电路老化的门替换方法  

Efficient method to mitigate NBTI-induced circuit degradation by gate replacement techniques

作　　者：梁华国[1] 陶志勇[2] 李扬[2,3] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009 [2]合肥工业大学计算机与信息学院,合肥230009 [3]江苏商贸职业学校信息系,南通226000

出　　处：《电子测量与仪器学报》2013年第11期1011-1017,共7页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(61274036;61106037;61106038);国家教育部博士点基金(20110111120012);安徽省高校自然科学研究重点项目(KJ2010A280);江苏省高校"青蓝工程"项目(2010121312)

摘　　要：45 nm工艺下,负偏置温度不稳定性(negative bias temperature instability,NBTI)效应是限制电路的性能的首要因素。为了缓解NBTI效应引起的电路老化,提出了1个基于门替换方法的设计流程框架和门替换算法。首先利用已有的电路老化分析框架来预测集成电路在其服务生命期内的最大老化,然后以门的权值作为指标来识别关键门,最后采用门替换算法对电路中的部分门进行替换。基于ISCAS85基准电路和45 nm晶体管工艺的试验结果表明,相对于已有的方法,采用文中的门替换方法,使得NBTI效应引起的电路老化程度平均被缓解了9.11%,有效地解决了控制输入向量(input vector control,IVC)方法不适用于大电路问题。Under 45 nm technology, the aging effect caused by negative bias temperature instability （NBTI） is the primary factor of limiting circuit performance. In order to mitigate the circuit aging effect caused by NBTI, a design flow framework and a gate replacement algorithm based on the gate replacement techniques are proposed. Firstly, the existing aging analysis framework is to predict the maximum circuit aging in its service lifetime. Secondly, the weight of gate is used as the index to identify the critical gate. Finally, a gate replacement algorithm is used to replace some gates in the circuit. The experimental results on ISCAS85 benchmark circuits and 45nm transistor model show that, compared with the existing techniques, the proposed gate replacement technique mitigates averagely 9.11% of circuit aging and solves effectively the problem that is the input vector control （IVC） method is not suitable for large circuits.

关 键 词：负偏置温度不稳定性 门替换 电路老化 

分 类 号：TP379.1[自动化与计算机技术—计算机系统结构] TN3[自动化与计算机技术—计算机科学与技术]