门控时钟技术在RTL功耗优化上的应用  

RTL Level Power Optimization using Clock Gating

作　　者：孙大成[1] 赵斌[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,合肥230088

出　　处：《中国集成电路》2013年第11期40-44,共5页China lntegrated Circuit

摘　　要：本文简单介绍了门控时钟技术应用于RTL级功耗优化的原理。针对具体的RTL实例,利用门控时钟技术实现了RTL的功耗优化。实验结果表明:在采用门控时钟技术后,设计的功耗得到了显著降低,而代价则是增加很小的芯片面积。This paper briefly introduces the conception of RTL level power optimization using clock gating with specific designs as an example. We use Sequential Clock-Gating to optimize designs for power by discovering and implementing clock gating, to generate optimized RTL code. The experiment shows better results that the system＇ s power is significantly reduced after RTL power optimization with little chip area adding.

关 键 词：门控时钟 功耗优化 

分 类 号：TN47[电子电信—微电子学与固体电子学]