AES加密引擎并行化设计与实现  

The Design and Realization of Parallelism of AES Encryption Engine

作　　者：苏阳[1] 

机构地区：[1]武警工程大学电子技术系,陕西西安710086

出　　处：《武汉大学学报（理学版）》2013年第5期471-476,共6页Journal of Wuhan University:Natural Science Edition

基　　金：国家自然科学基金(61103230);武警工程大学基础基金(wjy201312)资助项目

摘　　要：在自主设计AES-256加密算法IP核的基础上,提出了AES加密引擎和多密码引擎SoC的硬件结构,对它们内部的并行化设计进行了研究和分析.通过对加密引擎的逻辑综合和多密码引擎并行模块的定量分析发现,在160MHz的核心频率下,4个AES-256密码引擎并行模块受总线影响下的系统吞吐率为3.06Gb/s.与同类设计相比,本文的并行化设计占有更小的面积资源,具有更大的系统吞吐率,达到了多引擎并行化设计的目标.Based on the AES-256encryption algorithm IP core that designed by myself,this paper has proposed the hardware structure of AES encryption engine and multiple cipher engines SoC,studied and analyzed the parallelism design inside them.Through logic synthesis of encryption engine and parameter quantitative analysis of multiple cipher engines parallel module,we find the throughput affected by system bus of four AES-256cipher engines parallel module is 3.06Gb/s under 160MHz.In comparison with the congener design,the parallelism design proposed in this paper occupies less area resource and greater throughput,which can achieve the target of the parallelism design of multiple engines.

关 键 词：AES-256 IP核 加密引擎 多密码引擎 并行化 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]