基于APB总线接口的SPI协议IP核的设计与验证  

Design and verification of SPI IP Core based on APB Bus

作　　者：郭艾华[1] 

机构地区：[1]淮安信息职业技术学院,江苏淮安223003

出　　处：《无线互联科技》2013年第11期132-134,共3页Wireless Internet Technology

摘　　要：基于APB总线接口,设计了一种可灵活配置为Master/Slave模式、设置传输速率、支持DMA功能并适用于4种时钟模式的SPI协议IP核。首先介绍了SPI协议标准,然后详细说明了该IP核的系统结构、接口信号和子模块设计,并使用了Verilog HDL语言实现硬件设计。最后通过了FPGA时序仿真,验证了该设计的正确性。该IP核已成功用于一款通信芯片,证明了该IP核在实际工程中的可行性。Based on APB Bus, we designed an IP Core of SPI protocol, which could be configured as SPI Master or SPI Slave ,could set different transmission speed, could support DMA function, and could work in any one of the four clock modes. First,The paper introduces the standard of SPI protocol.Then, it describes the structure of the IP Core based on Verilog HDL. The module has already been verified by FPGA platform. Presently, the SPI IP Core had been applied in a chip to show the validity of this design in en^ineerin~ aPPlication.

关 键 词：SPI协议 IP核 Veri LOG HDL FPGA 

分 类 号：TN47[电子电信—微电子学与固体电子学]