面向CBC模式的AES高速芯片设计与实现  

Design and implementation of high-speed AES chip optimized for CBC modes

作　　者：刘楠[1] 陈迅[1] 李军伟[1] 

机构地区：[1]信息工程大学密码工程学院,河南郑州450004

出　　处：《电子技术应用》2014年第1期64-67,共4页Application of Electronic Technique

摘　　要：为以硬件方式高速实现AES密码算法,缩短整个芯片的关键路径,基于一种改进AES密码算法,在算法级对电路实现进行优化,将AES密码算法中字节代替变换与列混合变换进行合并,以查找表的方式实现这两种变换的一步变换。在支持密钥长度为128 bit、192 bit和256 bit AES算法的同时,支持分组密码工作中的ECB,CBC模式,提高了分组密码不同级别的安全性。在0.13μm CMOS工艺下,用Verilog硬件描述语言进行综合,仿真结果表明最高时钟频率可以达到781 MHz,在密钥长度分别为128 bit、192 bit和256 bit时,最大数据吞吐率分别可以达到9.9 Gb/s、8.3 Gb/s和7.1 Gb/s,占用面积38.5 KGates。For the purpose of implementing high-speed AES algorithm and reducing the critical path of the whole chip, this paper optimizes the circuits based on an improved AES algorithm in an algorithmic view. This paper merges the SubByte transform and the MixColumn transform together and implements it in the lookup table （LUT） approach. It can fully support AES-128/192/256 performance and meanwhile support both ECB and CBC modes improving different levels of the security of block cipher. Based on 0.13 μm CMOS technology, using Verilog hardware description language for synthesis, the simulation results show that 781 MHz clock frequency and up to 9.9/8.3/7.1Gb/s data throughput rate are achieved for AES-128/192/256 and the area cost is 38.5 KGates.

关 键 词：高速 高速加密标准 分组密码分组链接模式 分组密码电码本模式 

分 类 号：TN492[电子电信—微电子学与固体电子学]