一种多通道动态均衡先进先出缓存机制  

A multi-channel dynamic equilibrium FIFO caching mechanism

作　　者：谢廷婷[1] 彭鼎祥[2] 郑积仕[1] 

机构地区：[1]福建工程学院计算机与信息科学系,福建福州350108 [2]星网锐捷网络有限公司,福建福州350002

出　　处：《太赫兹科学与电子信息学报》2013年第6期897-901,共5页Journal of Terahertz Science and Electronic Information Technology

基　　金：福建工程学院校科研发展基金青年项目(GY-Z13011)

摘　　要：为了在多通道数据传输中实现各通道数据的均衡与高效传输,提出一种基于现场可编程门阵列(FPGA)的多通道动态先进先出缓存设计方法。该方法通过建立小型存储单元,动态维护各通道的数据传输状态,并采用数据库索引技术,为各通道数据高速、动态地分配缓存空间。本文以FPGA为平台,实现了该方法。仿真实验结果表明,该方法能通过较少的缓存设置,实现各个通道的均衡传输,节约存储资源,并提高各通道的数据传输效率。A multi-channel dynamic First Input First Output（FIFO） caching design method based on Field Programmable Gate Array（FPGA） is proposed in order to achieve a balanced and efficient transmission of the channel data in the process of multi-channel data transmission. The method, which is realized on FPGA platform, manages to dynamically maintain the data transmission status of each channel by establishing a small storage unit, and dynamically allocate the cache space for each channel data quickly by using the database indexing technology. Experimental results show that the method can achieve balanced transmission of each channel, save the storage resources and improve the efficiency of data transmission for each channel with fewer caching settings.

关 键 词：数据缓存 先进先出 存储单元 性能分析 现场可编程门阵列 

分 类 号：TN919.3[电子电信—通信与信息系统]