RTL综合中的格式判别  

Format Discriminant in RTL Synthesis

作　　者：谢巍[1] 袁媛[1] 张东晓[1] 刘明业[1] 

机构地区：[1]北京理工大学ASIC研究所,北京100081

出　　处：《计算机学报》2001年第1期99-105,共7页Chinese Journal of Computers

摘　　要：由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明该文提出的方法不但有效地区分了组合逻辑和时序逻辑 ,而且由于通过对组合?Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain. RTL synthesis, which converts behavior descriptions of RTL into structural descriptions of gate level, uses the theory of combinational logic synthesis and sequential logic synthesis into HDL (hardware description language). The base of RTL synthesis is format discriminance — distinguish combinational logic and sequential logic from behavior description, so as to use combinational logic synthesis and sequential logic synthesis separately to implement RTL synthesis. On the basis of analysis and summary of the disciplinarian of RTL behavior description and the limitation of logic synthesis, this paper discusses indispensability, feasibility, validity of format discriminance, and puts forward a simple method to implement format discriminance. This method can divide complex behavior descriptions into several assignment statement groups, using middle data format whose kernel is assignment statement and inner format (cube) accepted by logic synthesis, determine whether the entire assignment statement group is combinational logic or sequential logic on the basis of different conditions of those assignment statements in assignment statement group, and generate different level and independent function RT units. Thus we can use corresponding logic synthesis to deal with those RT units, and use combinational logic and sequential logic to implement RTL synthesis simply. At last the paper gives some examples. Through testing several examples and analyzing the results, it is confirmed that the method presented by this paper not only distinguishes combinational logic and sequential logic from behavior description, but also reuses combinational logic synthesis and sequential logic synthesis furthest. So the time used to develop RTL synthesis is reduced greatly. This method has been used in author's RTL synthesis system.

关 键 词：RTL综合 格式判别 时序逻辑 ASIC 专用集成电路 

分 类 号：TN492[电子电信—微电子学与固体电子学]