基于可变步长的访存延迟测量模型的研究与实现  

Research and implementation of memory latency measurement model based on variable stride

作　　者：毛席龙[1] 杨安[1] 吕高锋[1] 林琦[1] 程辉[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2014年第1期12-18,共7页Computer Engineering & Science

基　　金：国家973计划资助项目(2009CB320503)

摘　　要：评测访存延迟对于优化应用访存模式和数据放置有重要的指导意义,然而数据Cache、多线程、数据预取等技术却严重干扰了访存延迟测量的精度。设计并实现了基于可变步长的访存延迟测量模型,在一块空间内根据用户指定的步长创建访问序列环,循环访问这个序列得出平均时间,即为访存延迟。最后对Intel的通用处理器和飞腾处理器在不同数据大小、步长、线程数等情况下的访存延迟进行了测量比较,该模型能够显示存储层次并精确显示测量延迟。Evaluating the memory access latency has important significance for optimizing application patterns and data placement. However, cache, multi-threading, data prefetching and other techniques have serious interference with the accuracy of measurement of memory access latency. A measurement model based on variable strides is designed and implemented. According to user-specified strides, we create a sequence ring in a space, and circularly access this ring to obtain the average time as the memory access latency. Finally, we measure an Intel common processor and FT processor＇s memory latency by different data size, stride and thread, and make the data contrast with each other. This model can dis- play the memory hierarchy and display memory latency precisely.

关 键 词：内存延迟 可变步长 测量方法 SMT 多核处理器 飞腾处理器 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]