Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips  

作　　者：刘晓贤 朱樟明 杨银堂 王凤娟 丁瑞雪 

机构地区：[1]School of Microelectronics, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices

出　　处：《Journal of Semiconductors》2014年第1期121-128,共8页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61204044)

摘　　要：In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.

关 键 词：3D integration TSV signal reflection impedance matching S-PARAMETER 

分 类 号：TN402[电子电信—微电子学与固体电子学]