一种采用4bit MDAC的12bit流水线模数转换器  

A 12 bit Pipelined ADC with 4 bit MDAC

作　　者：庞瑞龙 赵毅强[1] 岳森[1] 秦国轩[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《半导体技术》2014年第2期93-97,102,共6页Semiconductor Technology

基　　金：国家重大科技专项资助项目(2012ZX03004008)

摘　　要：采用GF 0.18μm标准CMOS工艺,设计并实现了一种12 bit 20 MS/s流水线模数转换器(ADC)。整体架构采用第一级4 bit与1.5 bit/级的相结合的方法。采用改进的增益数模单元(MDAC)结构和带驱动能力的栅自举开关来提高MDAC的线性度和精度。为了降低子ADC的功耗,采用开关电容式比较器。仿真结果表明,优化的带驱动的栅自举开关可减小采样保持电路(SHA)的负载压力,有效降低开关导通电阻,降低电路的非线性。测试结果表明:在20 MS/s的采样率下,输入信号为1.234 1 MHz时,该ADC的微分非线性(DNL)为+0.55LSB/-0.67LSB,积分非线性(INL)为+0.87LSB/-0.077LSB,信噪比(SNR)为73.21 dB,无杂散动态范围(SFDR)为69.72 dB,有效位数(ENOB)为11.01位。芯片面积为6.872 mm2,在3.3 V供电的情况下,功耗为115 mW。A 12 bit 20 MS/s pipelined analog to digital converter （ADC） was designed and implemented using the GF 0.18μm CMOS process. The architecture is 1.5 bit/stage with a 4 bit in the first stage. A new multiplying digital-to-analog converter （MDAC） structure and a bootstrap switch with drive capability were adopted to improve the linearity and precision of the MDAC. Using the switchcapacitor comparator could effectively reduce the power consumption of the sub-ADC. Simulation results show that the bootstrap switch with drive capability could reduce the pressure of the sample-and-hold circuit （SHA） and effectively reduce the switch on-resistance and the linearity of the circuit. The measured results show that the presented ADC provides differential non linearity （DNL） of 0.55LSB/-0.67LSB and integral non linearity （INL） of 0. 87LSB/-0.077LSB. With signal to noise ratio （SNR） of 73.21 dB, it is able to deliver spurious free dynamic range （SFDR） of 69.72 dB, and achieves effective number of bits （ENOB） of 11.01 for 1. 234 1 MHz input at 20 MS/s sampling rate. The chip area is 6. 872 mm2, consuming 115 mW with a 3.3 V supply voltage.

关 键 词：模数转换器(ADC) 增益数模(MDAC) 带驱动栅自举开关 开关电容比较器 CMOS工艺 

分 类 号：TN792[电子电信—电路与系统]