一种基于CMOS亚阈值设计的低失调基准电路  

A low-offset reference circuits based on CMOS subthreshold

作　　者：苑乔[1] 邹光南[1] 张胜辉[1] 

机构地区：[1]航天恒星科技有限公司,北京100086

出　　处：《现代电子技术》2014年第5期149-151,共3页Modern Electronics Technique

摘　　要：基于工作在亚阈值区域的PMOS管,提出一种叠加结构的低失调带隙基准电路。该方法将传统基准电路中倍乘的失调电压转变为均方根的形式,有效降低了基准电路的失调电压。仿真表明该基准电路的输出电压为1.07 V,3σ范围内的失调电压为6.69 mV,温度特性为21.3 ppm/℃,PSRR为-56 dB。该电路在TSMC18工艺下成功流片。A superimposed structure bandgap reference circuits with low offset is composed,which was based on the PMOS working in subthreshold. Through transforming the multiplier format into root mean square , the offset voltage in traditional reference circuit is effectively reduced. The simulation showed that the output of the circuit is 1.07 V, and the offset voltage in the range of the 3σ is 6.69 mV,The temperature property is 21.3 ppm/℃ and PSRR is -56 dB. The circuit is tapped out suc-cessfully with TSMC18 process.

关 键 词：亚阈值 叠加结构 基准电路 失调电压 

分 类 号：TN45-34[电子电信—微电子学与固体电子学]