一种结合硬件特征的并行内存故障检测方案  

A Parallel Memory Fault Detection Scheme Combined with Hardware Characteristic

作　　者：胡蝶[1] 吴俊敏[1,2] 

机构地区：[1]中国科学技术大学计算机科学与技术学院,合肥230027 [2]中国科学技术大学苏州研究院,苏州215123

出　　处：《计算机工程》2014年第3期310-314,共5页Computer Engineering

基　　金：国家自然科学基金资助项目(61272132);中央高校基本科研业务费专项基金资助项目(WK0110000020);中国科学院计算技术研究所国家重点实验室开放基金资助项目(CARCH201204)

摘　　要：针对March类内存检测算法越来越复杂、检测时间越来越长,且更适用于对嵌入式内存芯片的检测等问题,提出一种结合硬件特征的并行内存故障检测方案。该方案包括2种并行检测方法:(1)根据DDR2的结构和工作原理设计的芯片级并行,可以并行检测一个DDR2内部的多个内存芯片。(2)根据访存控制器的结构和工作原理设计的访存控制器级并行,可并行检测多个DDR2内存条。对于芯片级并行,访存带宽越大,即并行检测的芯片个数越多,并行效果越好,从1个芯片到并行检测8个芯片,内存的检测时间几乎是呈线性递减的。对于访存控制器级并行,访存控制器数量越多并行效果越好,从1个LMC到2个LMC,内存的检测时间几乎减少了一倍。实验结果表明,2种并行检测方法不仅能够成倍加快检测速度,而且更适用于用户对内存的检测。March algorithms are designed very complex, and they are designed to be used to test memory chips, does not apply to the user. In order to solve above problems, this paper presents a parallel memory test method which utilizes the hardware features. It includes two parallel methods： one is chips-level parallel method which is designed according to the working principle of DDR2, and it can detect several memory chips. The other is Local Memory Controller（LMC）-level parallel method which is designed according to the working principle of memory controller, and it can detect several DDR2 memories. For chips-level parallel method, if more chips can be tested, the test time is faster. From testing one chip to eight chips, the test time is almost linearly decreasing. For LMC-level method, if there are more LMCs, the time is faster. From one LMC to two LMCs, the test time is reduced by almost doubled. Experimental results show that this method can greatly reduce the test time of the two algorithms, while still allow users to test memory.

关 键 词：故障模型 MARCH算法 DDR2内存条 芯片级并行 访存控制器级并行 

分 类 号：TP306[自动化与计算机技术—计算机系统结构]