ULSI后端设计低功耗技术研究  

Study on Power Reduction Techniques for Physical Design of ULSI

作　　者：杨兵[1,2] 张玲[2] 魏敬和[2] 于宗光[1,2] 

机构地区：[1]江南大学物联网学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2014年第1期10-13,共4页Microelectronics

基　　金：江苏省"333工程"科研资助项目(BRA2011115)

摘　　要：提出一种新的ULSI后端设计低功耗流程,重点分析了版图压焊点位置摆放、宏单元位置规划、电源网络布局及物理综合功率优化设计等四项关键技术。采用SMIC 0.18μm 1P6M自对准硅化物CMOS工艺,设计了一种新型雷达SoC芯片,电路版图尺寸为7.825mm×7.820mm,规模为200万门,工作频率为100MHz。实验结果表明,采用低功耗物理设计技术后,芯片功耗降低12.77%,满足350mW功耗的设计要求。该电路已通过用户的应用验证,满足系统小型化和低功耗需求。A new technique for power reduction of deep sub-micron CMOS USLI in physical design stage was proposed. Placement of pads and location plan of macro calls in layout, and power planning and power optimization in physical synthesis were analyzed in particular. Based on SMIC＇s 0.18 μm 1P6M salicide CMOS process, an SoC operating at 100 MHz with about 2 million gates and 7. 825 mm× 7. 820 mm layout size was designed. Experimental results showed that, by using the proposed power reduction technique, power consumption of the chip was reduced by 12. 77 %, which met the design target of 350 roW.

关 键 词：USLI 低功耗技术 后端设计 SOC CMOS 

分 类 号：TN402[电子电信—微电子学与固体电子学]