一种多通道ARINC429总线协议IP核的设计与实现  

Design and Research Implementation of Multichannel ARINC429 Bus Protocol IP Core

作　　者：魏永升 向新[1] 王占领[1] 

机构地区：[1]空军工程大学航空航天工程学院 [2]北空航管中心

出　　处：《微电子学与计算机》2014年第3期78-81,共4页Microelectronics & Computer

基　　金：航空科学基金(20101996009)

摘　　要：设计了基于FPGA的ARINC429总线协议IP核.给出了IP核的总体设计及工作原理.在设计时采用功能模块的方法,分别设计数据协议处理模块、缓冲模块、定时模块等部分.充分利用同步时钟方法,提高了可靠性,有效解决了数据间干扰和亚稳态问题.经验证表明IP核的功能符合设计要求.最后经过物理验证,能够正确实现收发功能,且满足特定场合的应用.This article designs the ARINC429 bus protocol IP core based on FPGA .The integrated design and the operational principle of the IP core are given . With modular method , this design integrates the data protocol processing module ,the data buffer module and timing module in one FPGA chip .Using the independent methods and synchronization ways of designing the encoder and decoder ,it improves the reliability and lessens the interference between the data efficiently ,and resolves the metastability issue .The validating result indicates that the functions of IP core could fit the designing demand .Through physical testing at last ,the IP core can achieve every function and could be applied in series of situation .

关 键 词：ARINC429总线 IP核 FPGA 

分 类 号：V243.1[航空宇航科学与技术—飞行器设计]