基于Mini-LVDS技术的TFT-LCD时序控制器的设计  

Design of TFT-LCD timing controller based on mini-LVDS technology

作　　者：刘杰[1] 程松华[1] 张永栋[1] 李曙新[1] 

机构地区：[1]天马微电子股份有限公司研发中心,广东深圳518118

出　　处：《液晶与显示》2014年第2期238-244,共7页Chinese Journal of Liquid Crystals and Displays

摘　　要：为了实现基于FPGA的具有Mini-LVDS接口的TFT-LCD时序控制器,对TFT-LCD的时序控制器、Mini-LVDS技术的数据排列方式和FPGA的功能进行了研究。通过对Mini-LVDS的数据排列方式的研究,提出了独特的数据处理方法。利用FPGA内嵌的SRAM,设计了一种并行转串行的转换器,把一行的数据分成前半部分和后半部分并同时向外输出;利用D触发器、延时的方法实现了相邻二点的数据串并转换;综合利用移位寄存器、串行加法器和DDR技术,设计了一种8∶1的并串转换电路,实现了子像素内数据的并串转换。利用Xilinx公司的FPGA的输出宏单元,设计了把CMOS逻辑电平信号转换为Mini-LVDS逻辑电平信号的数据发送器。利用Xilinx公司的FPGA的时钟宏单元块,探讨并解决了多时钟的问题。通过研究Mini-LVDS和时序控制器的特性,提出了复位信号的产生方法和相对应的数据处理方法。利用此方法设计出的具有Mini-LVDS接口的时序控制器已应用于本公司的分辨率为1 280×1 024的产品中,数据的传输频率达108MHz,颜色深度为24bit。这个产品的显示画面清晰,过渡自然。利用此方法设计的TFT-LCD的时序控制器基本符合稳定可靠、抗干扰能力强等要求。In order to realize the Timing Controller of TFT-LCD with Mini-LVDS interface based on FPGA, data arrangement of technology of Mini-LVDS and the timing controller of TFT-LCD, the function of FPGA are investigated . By studying data arrangement of Mini-LVDS, a special method of data processing was proposed. A parallel to serial converter was designed by using SRAM embedded in FPGA, the data in a row was divided into a front half part and a latter half part and the two parts of data were put out at the same time. The data of two adjacent points was turned from serial to parallel by using D trigger and the method of delay. By using shift register, serial adder and DDR technology, an 8 ： 1 converter was designed and the data in a sub-pixel was turned from parallel to serial. Output Logic Macro cell in FPGA of Xilinx was used in the design of a data transmitter that turned the CMOS logic level signal into Mini-LVDS logic level signal. The problems of multiple clocks were discussed and solved by using clock macro blocks in FPGA of Xilinx. By studying the characteristics of Mini- LVDS and Timing Controller, the method of generating reset signal and the corresponding method of the data processing were presented. The timing controller of TFT-LCD with Mini-I.VDS interface has been applied to products of our company with resolution of 1 280X 1 024 , the frequency of its data is 108 MHz, and its color depth is 24 bit. The picture of the product is clear and natural. The timing controller of TFT-IJCD can satisfy the system requirements of strong anti-jamming and stabilization.

关 键 词：时序控制器 Mini-LVDS FPGA VERILOG HDL 

分 类 号：TN141.9[电子电信—物理电子学]