晶圆切割和随机缺陷驱动的掩模设计方法  

Wafer dicing and random defect driven reticle design

作　　者：叶翼[1] 朱椒娇[1] 史峥[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《华中科技大学学报（自然科学版）》2014年第3期37-41,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家十一五重大科技专项基金资助项目(2008ZX01035-001-06)

摘　　要：针对现有掩模设计方法的不足,提出了同时考虑晶圆切割和随机缺陷的掩模设计方法.在预估边到边晶圆切割引起的成品率丢失的同时,将随机缺陷引起的成品率丢失也纳入了设计参考量.对掩模上芯片进行布局规划的阶段,使那些由于随机缺陷造成成品率丢失较高的芯片在布局规划的目标函数中拥有较大的权重.这些芯片会在模拟退火算法迭代的过程中被自动放置在相应的与其他芯片较少切割冲突的位置,避免了后期晶圆切割对其产量造成的损失.此方法均衡了芯片之间的产量,在满足各个芯片需要产量的前提下,减少了生产所需的晶圆数量.与最小化掩模面积的设计方法和只考虑晶圆切割的设计方法比较,该方法使生产所需要的晶圆数量分别减少了15.22%和7.14%.In order to cover the shortages in existing reticle design methods,a reticle design method was proposed to consider both the yield loss caused by wafer dicing and the yield loss caused by random defect.During the stage of reticle floorplanning,chips with higher yield loss rate caused by random defect had higher penalty in the objective function;therefore,through simulated annealing,they were automatically placed at a proper position of the reticle to avoid yield loss caused by wafer dicing conflict.This mechanism balances the production volumes of chips.On the premise of ensuring required production volumes,it decreased the numbers of wafers required.Compared with the method minimizing the area of reticle and the method considering only wafer dicing,the proposed method decreases the numbers of the wafers by 15.22%and 7.14%,respectively.

关 键 词：集成电路制造 计算机辅助设计 模拟退火 掩模设计 晶圆切割 随机缺陷 成品率模型 

分 类 号：TN4[电子电信—微电子学与固体电子学]