基于OMAP处理器的核间通信机制设计与实现  

Design and Implementation of Inter-core Communication Mechanism Based on OMAP Processor

作　　者：冯强[1,2] 胡毅[2,3] 于东[2,3] 陆小虎[1,2] 

机构地区：[1]中国科学院大学,北京100049 [2]中国科学院沈阳计算技术研究所高档数控国家工程研究中心,沈阳110168 [3]沈阳高精数控技术有限公司,沈阳110168

出　　处：《计算机工程》2014年第4期281-286,共6页Computer Engineering

基　　金：国家科技重大专项基金资助项目"开放式数控系统支撑技术创新平台建设"(2011ZX04016-071)

摘　　要：为满足嵌入式多核数控系统高速、高精的应用需求,针对现有多核通信延迟过高、通信数据量过小等不足,研究基于ARM与DSP双核架构嵌入式数控系统,设计并实现一种基于该数控系统平台的多核数据通信机制。该通信机制基于共享内存实现,包括硬件驱动实现、内存划分、通信同步、共享缓存池建立以及通信协议搭建等关键部分。针对双核间数据传输延迟和数据传输量2个影响系统性能的重要参数开展实验测试,并于实际数控系统环境进行应用测试,结果表明,该通信方法可满足ARM与DSP双核架构的嵌入式数控系统2 MB数据通信量与20 ms通信延迟的性能需求。In order to meet the application needs of embedded multi-core, high-speed and high-precision numerical control system, owing to the high latency, low communication capacity of current multi-core communication, this paper studies the design of embedded numerical control system based on ARM and DSP dual-core architecture, designs and implements a multi-core data communication mechanism based on the numerical control system platform. The communication mechanism is based on shared memory, including hardware driver realization, memory division, communication synchronization and the establishment of a shared cache pool and communication protocol. It completes the measurement of dual-core data transmission latency and data transmission capacity, which affects system performance, and carries out the application test. The results prove that this design can meet the performance requirements of 2 MB data communications volume and 20 ms communication delay of the embedded ARM and DSP dual-core architecture numerical control system.

关 键 词：嵌入式数控系统 异构处理器 多核通信 共享内存 通信延迟 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]