多FIFO灵活定制SDRAM控制器设计  

Flexibly Customized Multi-channel FIFO Design for SDRAM Controller

作　　者：丁国栋[1] 刘昌华[1] 

机构地区：[1]武汉轻工大学数学与计算机学院

出　　处：《电子世界》2014年第7期143-145,共3页Electronics World

摘　　要：针对SDRAM控制器设计复杂且可复用性低的特点,基于VerilogHDL提出了一种简单且可灵活定制异步FIFO的SDRAM控制器实现。图像预处理时经常会用到SDRAM来作为缓存,SDRAM的工作频率很高,所以一般会用异步FIFO缓存数据匹配它的频率,但是每次都重新设计FIFO的控制显然太繁琐。本设计结合FPGA的特点一方面简化SDRAM的控制时序提高了系统性能,另一方面在控制器中嵌入多路异步FIFO,当面对不同的设计需要时只需给设计关心的异步FIFO加载上数据、时钟、深度以及地址则可。既节约了逻辑资源又实现了重复使用的目的为后续设计节省了时间。This paper proposes a simple and flexibly customized asynchronous FIFO for SDRAM controller based on FPGA, it solves the problem that the SDRAM controller design is complexed and low reusahle.SDRAM is often used in image preprocessing, and its frequency is very high, so multiple asynchronous FIFO are used for data buffer matching its working frequency.But the control of FIFO is redesigned every time, which is too complicated.The design simplifies the timing control of the SDRAM, which improves the system＇s performance and embeds multi-channel asynchronous FIFO.when faced with a different design needs, the designer just loads the data, clock, depth, and the address on the asynchronous FIFO.It saves logic resources and achieves the purpose of reuse which saves time for the subsequent design.

关 键 词：灵活定制 异步FIFO 多通道 SDRAM VERILOGHDL 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构]