基于附加信号回波抵消的FPGA实现  

FPGA Implementation of Echo Cancellation Based on Additional Signal

作　　者：王振朝[1] 包伟华[1] 李会雅[1] 杨建坡[2] 

机构地区：[1]河北大学电子信息工程学院,河北保定071002 [2]奥维通信股份有限公司,广东510000

出　　处：《激光杂志》2014年第4期35-37,共3页Laser Journal

基　　金：奥维通信股份有限公司委托研究项目"移动通信直放站关键技术研究"的子课题(2010-19);2012年保定市科学技术研究与发展指导计划(12ZG016)

摘　　要：针对基于附加信号回波抵消在硬件设计中出现的迭代误差累积导致信道估计不准确和耗费大量FPGA资源的问题,对算法进行了改进。从主径开始估计回波信道的方法,提高了信道估计精度和减少了FPGA资源消耗。然后,在FPGA平台上用硬件语言Verilog HDL对此回波抵消系统加以实现。仿真结果表明此设计在回波抵消方面具有良好的效果。For the problem that iteration error accumulation which leads to channel estimation inaccurate and consumes a lot of FPGA resources occurs in the hardware design of echo cancellation based on additional signal, it improved the algorithm. The method of estimating echo channel from the main path has improved the accuracy of channel estimation and reduced the FPGA resource con- sumption. Then it achieved the echo cancellation system using Verilog HDL language on FPGA. Simulation results show that the de- sign has better effect of echo cancellation.

关 键 词：附加信号 回波抵消 迭代误差 主径时延 FPGA实现 

分 类 号：TN911.7[电子电信—通信与信息系统]