基于SOI CMOS工艺的LVDS驱动器设计  

Design of the LVDS Driver Based on the SOI CMOS Process

作　　者：卜山 周玉梅[1] 赵建中[1] 刘海南[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2014年第5期326-329,334,共5页Semiconductor Technology

基　　金：国家高技术研究发展计划(863计划)资助项目(2011AA010403)

摘　　要：基于绝缘体硅(SOI)0.35μm工艺实现了一款满足IEEE 1596.3和ANSI/TIA/EIA-644工业标准的低压差分信号(LVDS)驱动器芯片。全芯片分为预驱动模块、输出驱动模块、共模反馈模块、使能模块和偏置模块。提出了一种具有低输入电容输出驱动模块电路结构,经仿真验证可有效降低LVDS预驱动模块30%的功耗,同时降低29%的信号延时。芯片利用共模反馈机制控制输出信号的共模电平范围,通过环路补偿保证共模反馈电路的环路稳定性。芯片使用3.3 V供电电压,经Spice仿真并流片测试,输出信号共模电平1.23 V,差分输出电压347 mV,在400 Mbit/s数据传输速率下单路动态功耗为22 mW。A low voltage differential signaling （LVDS） driver based on 0.35 μm silicon on insula- tor （SOI） CMOS process was demonstrated with the full stage compliance of IEEE 1596.3 and ANSI/ TIA/EIA-644 standard. The LVDS driver is divided into the following modules as pre-driver module, output-driver module, common mode feedback module, enable module and bias module. An output- driver module circuit with low input capacitance was introduced, simulation tests show 30% reduction in power and 29% reduction in signal delay of the pre-driver module. The output offset voltage was con- trolled by the common mode feedback module, and the compensation was introduced to make the feed- back loop stable. The test results of the LVDS driver show that the output offset voltage is 1.23 V, the differential output voltage is 347 mV and the dynamic power of the driver is 22 mW at the 400 Mbit/s da- ta rate and the 3.3 V supplied voltage.

关 键 词：低压差分信号传输(LVDS) 绝缘体硅(SOI) 共模反馈 低输入负载 环路补偿 

分 类 号：TN432[电子电信—微电子学与固体电子学]