一种高速采样/保持电路的设计与分析  

Design and Analysis of a High Speed Sample-and-Hold Circuit

作　　者：谭智琴 王永禄[2] 张龙生[1] 张正平[2] 刘明[2,3] 冯小刚[1,2] 徐辉[1,2] 

机构地区：[1]重庆邮电大学,重庆400065 [2]模拟集成电路重点实验室,重庆400060 [3]重庆大学,重庆400044

出　　处：《微电子学》2014年第2期163-166,共4页Microelectronics

摘　　要：介绍了一种高速采样/保持电路,分析了电路的非线性效应。该电路基于0.18μm GeSi BiCMOS工艺,采用全差分开环结构,通过射极负反馈和前馈误差放大器来改善输入缓冲放大器的线性度。采用交换式射极跟随器开关,可以提高电路的采样速度,减小谐波失真。三级级联的输出缓冲减小了下垂率,并增大对后级电路的驱动能力。在3.3V电源电压和500fF负载电容下,采用Cadence Spectre进行仿真分析。结果显示,在相干采样模式下,采样率为1.28GS/s时,在27℃温度下,整个电路的SFDR为77dB,THD为-68.38dB,功耗为133mW;采样率为2.5GS/s时,各个温度下均满足8位的精度要求,可用于高速A/D转换器。A high speed sample and hold circuit was presented,and its non-linearity was analyzed.The circuit was designed with differential open-loop stricture based on 0.18μm GeSi BiCMOS process.The linearity of input buffer was improved by using emitter degeneration and forward error amplifier.Switched emitter follower was adopted to meet improve sampling rate and reduce total harmonic distortion.The output buffer was implemented with 3-stage structure to reduce droop rate and enhance the capability to drive follower circuit.The circuit was simulated with Spectre of Cadence at 3.3Vpower supply and 500fF load capacitance.Results showed that,in coherent sampling mode,and at 27 ℃,the circuit had an SFDR of 77dB and THD of-68.38dB at 1.28GS/s sampling rate with a total power of 133mW,and at 2.5GS/s,it met specifications for 8-bit resolution at different temperatures.

关 键 词：采样 保持电路 GESI BICMOS 交换式射极开关 A D转换器 

分 类 号：TN433[电子电信—微电子学与固体电子学]