A power efficient 1.0625–3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications  

作　　者：HOU ZhongYuan YANG Fan LIU JunHua ZHANG Xing 

机构地区：[1]Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University

出　　处：《Science China(Information Sciences)》2014年第6期178-187,共10页中国科学（信息科学）（英文版）

摘　　要：A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel（FC）,Peripheral Component Interconnect Express（PCIe）,and RapidIO applications.To support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated（SST）transmitter（TX）,a passive receiver（RX）equalizer,a dual-loop phase locked loop（PLL）and a mixed signal clock and data recovery（CDR）unit.The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter,and a passive equalizer that achieves 4 dB transmission in the receiver.The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference.A CDR with a phase interpolator（PI）is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm.The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm2.With supply voltages of 1.2 V and 3.3 V,the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at3.125 Gb/s.A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel（FC）,Peripheral Component Interconnect Express（PCIe）,and RapidIO applications.To support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated（SST）transmitter（TX）,a passive receiver（RX）equalizer,a dual-loop phase locked loop（PLL）and a mixed signal clock and data recovery（CDR）unit.The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter,and a passive equalizer that achieves 4 dB transmission in the receiver.The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference.A CDR with a phase interpolator（PI）is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm.The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm2.With supply voltages of 1.2 V and 3.3 V,the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at3.125 Gb/s.

关 键 词：serial transceiver MULTI-STANDARD power efficiency SST CDR 

分 类 号：TN859[电子电信—信息与通信工程]