一种高速LVDS接口的存储器设计  

A New Memory Design Technic for High-Speed LVDS Interfaces

作　　者：马强[1] 宋何娟[1] 周乐[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,安徽合肥230088

出　　处：《中国集成电路》2014年第5期30-34,共5页China lntegrated Circuit

摘　　要：此存储器设计是基于已有SRAM基础上增加外围LVDS接口和一些数据处理电路而改进的一种新型存储器。它应用一些有LVDS接口的高速AD上,可直接接收AD过来的数据,写入到存储器中,然后通过LVDS接口进行读操作。此存储器的时钟为500MHz,存储容量为4Mbits,支持数据单沿采样和双沿采样,采用QFN88封装,面积2.5mm*3mm。The new memory design introduced in this paper is based on the application of already existing SRAM combined with extra peripheral LVDS interfaces and data processing units. This new design can be widely in the case of high-speed AD circumstances, with data transmitted directly from AD, written into memory and further read through LVDS interfaces. The memory is fully capable of both single and double edge samwith the main working frequency 500MHz, and the memory capability is 4Mbits. The chip is packaged with technology with area of 2.5mm＊3mm.

关 键 词：LVDS接口 存储器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]