高速RS编码器的设计与实现  

Design and Implementation of High speed RS Encoder

作　　者：于伟[1] 李文[1] 鞠德航[1] 

机构地区：[1]西安空间无线电技术研究所

出　　处：《信号处理》2000年第4期291-296,共6页Journal of Signal Processing

摘　　要：研究高速ＲＳ码编码器的设计与实现问题．给出了最优对偶基的计算方法，研究了用对偶基下的bit-parallel乘法器构成ＲＳ系统码编码器．用ＦＰＧＡ实现了高速ＲＳ编码器，仿真结果表明编码器的吞吐率可以达到１２５Ｍｂｙｔｅｓ／ｓ．design and implementation of high speed RS encoder is conerned over the extended dual basis THe method of obtaining the optimal dual basis is introduced and the optimal dual basis is calculated of the CCSDS RS code.Instead of the bit-serial encoder,a bit-parallel dual basis RS endoer is designed for high speed applications.The results obtained by timing simulation show that the throughput of the prototype can be up to 125Mbytes/s.

关 键 词：RS编码器 对偶基 高速实现 

分 类 号：TN962[电子电信—信号与信息处理]