基于FPGA的异步流水乘法器设计的教学方案  

Teaching Scheme for Design of Asynchronous Pipeline Multiplier Based on FPGA

作　　者：李贞妮[1] 李晶皎[1] 金硕巍[1] 

机构地区：[1]东北大学信息科学与工程学院,辽宁沈阳110819

出　　处：《电气电子教学学报》2014年第2期57-59,共3页Journal of Electrical and Electronic Education

基　　金：中央高校基本科研业务费青年教师科研启动基金资助项目(N100304008)

摘　　要：本文以异步流水乘法器的设计为例,介绍了利用FPGA进行异步电路设计的思路及方法。本设计采用两段握手协议实现异步流水乘法器,将其分解为三个核心模块:信号分支模块、异步移位模块和异步加法器模块。本文具体说明了利用硬件描述语言实现异步乘法器的方法和步骤,通过Modelsim软件进行功能仿真,并下载到Genesys板卡上进行系统测试。该教学方案有助于学生理解并掌握异步电路设计方法。This paper takes the example of asynchronous pipeline multiplier to illustrate the design method of asyn- chronous circuit based on FPGA. Two handshake protocol is used. The asynchronous multiplier is divided to three modules： signal branching module, asynchronous shift module and asynchronous adder module. The method and steps to realize the asynchronous multiplier is explained, functional simulation is performed using Modelsim, and then the configuration bit stream is downloaded to the Genesys for system testing. The teaching scheme accords can help students to master the asynchronous circuit design method.

关 键 词：FPGA 异步电路 流水乘法器 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]