循环汉明码编译码器的设计与FPGA实现  

Design and implementation of cyclic Hamming code encoder/decoder based on FPGA

作　　者：王书省[1] 贺占权[1] 张少甫[1] 肖长春[1] 曹旸[1] 

机构地区：[1]航天恒星科技有限公司,北京100086

出　　处：《现代电子技术》2014年第10期127-131,共5页Modern Electronics Technique

摘　　要：分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。Based on characteristics analysis of cyclic codes,a design scheme of cyclic Hamming code encoder/decoder is proposed. In the encoder/decoder,a division circuit is adopted for encoding,and a Meggitt decoder is adopted for decoding, which are easy to be applied to engineering implementment. The encoder/decoder,which is suited for （255,247） and its cyclic Hamming code of arbitrarily-truncated codes,and has higher code rate,was implemented on FPGA by means of Verilog HDL. Some optimization techniques in the design process are given. The simulation and testing results of the encoder/decoder are of-fered in this paper. The encoder/decoder can operate at high speed and has short decoding delay. Its max working clock frequen-cy is higher than 270 MHz in Virtex-5 chip. The encoder/decoder can be applied in digital communication systems that have defi-nite error number. Its BER can be reduced efficiently. The encoder/decoder has high practical value.

关 键 词：循环码 汉明码 编译码器 FPGA 

分 类 号：TN914-34[电子电信—通信与信息系统]